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By Sergio Franco

ISBN-10: 0078028191

ISBN-13: 9780078028199

This textbook is meant for EE majors envisioning business careers in analog electronics. Analog integrated-circuit (IC) designers, product, procedure, and reliability engineers, try out and test-development engineers, analog purposes, advertising, and customer-support engineers are consistently in powerful call for.

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25vI 1 6 V for vI . 18b shows the circuit’s VTC. Clearly, we have three separate regions of operation. Within each region, the VTC is a straight segment whose analytical expression is obtained by drawing the corresponding equivalent circuit, as per Fig. 19, and subjecting it to elementary linear analysis techniques. This is typical of diode circuits. 20 shows the waveshaping effect of the circuit of Fig. 18 upon a triangular wave. Here, the aim is to compress the top and the bottom of the triangle to approximate a sine.

At which peak of vI does v2 come within about 10% of 20 V? 1% of 20 V? Ans. For 10%, k 5 3. For 1%, k 5 6. The principle at the basis of the voltage doubler can be generalized to achieve higher voltage-multiplication factors. 25 shows a voltage quadrupler, whose waveforms are displayed in Fig. 26. 8) or v4 5 40 V in the present example. The reader is encouraged to trace through each waveform in detail to develop a feel for the workings of this clever circuit. Voltage multipliers find application in integrated circuits, where it is desired to synthesize specific voltages to bias different on-chip circuits, starting out with a single supply voltage such as that provided by a rechargeable battery.

47b) is the zero-bias (v 5 0) value of Cj and m, called the grading coefficient, is 1⁄2 in the present case, which assumes an abrupt junction. Practical junctions often have a graded doping profile, in which case it can be shown2 that a more appropriate value is m 5 1⁄3. The actual value of m can be found experimentally by measuring Cj for different values of v and then using data-interpolation to indirectly find m. The voltage dependence of Cj is depicted in Fig. 41b. 42 (a) The junction capacitance Cj, and (b) its parallel-plate equivalent.

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Analog Circuit Design: Discrete & Integrated by Sergio Franco


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